Lenovo LF80565QH0254M Arkusz Danych Pobierz pdf (Strona 54)

Electrical Specifications

54 Document Number: 318080-002

Notes:

1. Ta = T40 (FERR# Valid Delay from STPCLK# Deassertion).

2. FERR# / PBE# is undefined from STPCLK# assertion until the Stop-Grant acknowledge is driven on the

FSB. FERR# / PBE# is also undefined for a period of Ta from STPCLK# deassertion. Inside these undefined

regions, the PBE# signal is driven. FERR# is driven at all other times.

Figure 2-25. FERR#/PBE# Valid Delay Timing

BCLK

STPCLK#

System bus

FERR#/PBE#

Ack

FERR# undefined FERR#

PBE# undefined

Figure 2-26. VID Step Timings

VID

n n-1 m+1m

...

Ta = T84: VID Down to Valid V

(max)

Tb = T82: VID Down to Valid V

(min)

Tc = T85: VID Up to Valid V

(max)

Td = T83: VID Up to Valid V

(min)

(max)

(min)

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Lenovo LF80565QH0254M Arkusz Danych Strona 54